Many devices that receive high-speed digital bit streams utilize a technique referred to as “clock recovery” in which a receive clock for processing the bit stream is not communicated separately from the bit stream but instead generated from the transmitted bit stream. Often, the receiving device utilizes a phase-locked loop (PLL) circuit to generate the receive clock for processing the received digital bit stream. A PLL circuit relies on data transitions in the received digital bit stream to generate the receive clock at the proper frequency and phase transitions. For example, the PLL circuit compares the time when a data transition occurred in digital bit stream to a time when a rising or falling edge occurred in the generated receive clock. The PLL circuit controls the phase of the receive clock based on the comparison to generate a phase-locked receive clock that aligns with the transitions with the communicated data.